A copy of the selected machine is saved in SRC (with postfix _save ) and an SLIB version of the machine created in the library: files are copied from the current ANL CFG and TYP directories into the corresponding SLIB directories (so you must have write permission in that directory).
The newly-created library machine is not removed from the current development.
Two options are available:
The former option enables hand-written VHDL code modules to be created in the system library, and a .vhd file is created (if a .vhd_save file does not exist in SRC - otherwise that file is used as the starting point) and loaded into the editor.
After the file has been edited, Two further options are available (apart from Cancel which saves the file in SRC with a _save postfix, so that it may be used, if required, in a subsequent attempt as described above):
In particular, the analysis should demonstrate that module parameters and signals are correctly identified and that for each operation, it's header, variables and body are successfully determined.
An iteration of Edit-Analyse Code Module may be employed until the correct analysis is produced, when the Create VHDL SLIB Construct option should be selected to copy the code, as well as the AMN constructs described above, into the VHDL SLIB directories.
A copy of the code (as well as the
machine) is saved in SRC (with postfix _save ).