The VHDL Translator (trl)

The VHDL Translator is invoked from the VHDL Environment and is applicable to all constructs which are currently analysed, but not translated.

Overview

Only the Simple Modules ( _SM ) and the Compound Modules ( _CM ) can be subjected to translation into VHDL.

Both types of Modules will be translated into a VHDL 'Entity-Architecture-Module'. The VHDL resulting from the translation of a Compound Modules consist of the collection of instantiated 'Entity-Architecture-Module', resulting from the separate translation of its component Simple Modules.

Process, Signal and Package Modules are not separately translated, but they are used to guide the translation of the Simple Modules of which the form a part; either because they are INCLUDED ( Process and Signal Modules) or they are SEEN ( Package Modules ). The code contributed by the Processes, Signals and Packages are 'in-lined' into the 'architecture-statement', of the Simple Module of which they are a component part.

The `most concrete' refinement of each machine is used when the VHDL code is constructed. Often this will be the specification ( .mch ) but if a refinement ( .ref ) or implementation ( .imp ) exists (and is analysed), it will be taken instead.

During translation the generic assignment of VHDL System Library machines ( <-- ) is converted into signal assignment ( <= ) or variable assignment ( := ), determined by the using module.

A full on-line help listing is available in the Contents Page Also available in the form of a complete Index. Blogo